verilator/test_regress/t/t_var_nonamebegin.out

$version Generated by VerilatedVcd $end
$date Tue Jul 24 18:46:01 2012
 $end
$timescale 1ns $end

 $scope module top $end
  $var wire  1 # clk $end
  $var wire  1 $ reset_l $end
  $scope module t $end
   $var wire  1 # clk $end
   $var wire  1 % inmod $end
   $var wire 32 & rawmod [31:0] $end
   $var wire  1 $ reset_l $end
   $scope module genblk1 $end
    $var wire 32 ' ingen [31:0] $end
   $upscope $end
   $scope module unnamedblk1 $end
    $var wire 32 ( upa [31:0] $end
    $scope module d3nameda $end
     $var wire 32 ) d3a [31:0] $end
    $upscope $end
   $upscope $end
   $scope module unnamedblk2 $end
    $var wire 32 * b2 [31:0] $end
    $scope module b3named $end
     $var wire 32 + b3n [31:0] $end
    $upscope $end
    $scope module unnamedblk3 $end
     $var wire 32 , b3 [31:0] $end
     $scope module unnamedblk4 $end
      $var wire 32 - b4 [31:0] $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


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