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70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Mike Popoloski.
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interface foo_intf
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(
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input x
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);
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endinterface
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module foo_subm
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(
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input x
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);
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endmodule
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module t ();
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localparam N = 3;
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wire [2:0] X = 3'b110;
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// Should not cause LITENDIAN warning, as no harm in array selections.
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// verilator lint_on LITENDIAN
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foo_intf foo1 [N] (.x(1'b1));
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foo_subm sub1 [N] (.x(1'b1));
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// Will cause LITENDIAN warning?
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// verilator lint_off LITENDIAN
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foo_intf foos [N] (.x(X));
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foo_intf fool [1:3] (.x(X));
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foo_intf foom [3:1] (.x(X));
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foo_subm subs [N] (.x(X));
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foo_subm subl [1:3] (.x(X));
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foo_subm subm [3:1] (.x(X));
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initial begin
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// Check numbering with 0 first
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// NC has a bug here
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if (foos[0].x !== 1'b1) $stop;
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if (foos[1].x !== 1'b1) $stop;
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if (foos[2].x !== 1'b0) $stop;
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//
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if (fool[1].x !== 1'b1) $stop;
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if (fool[2].x !== 1'b1) $stop;
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if (fool[3].x !== 1'b0) $stop;
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//
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if (foom[1].x !== 1'b0) $stop;
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if (foom[2].x !== 1'b1) $stop;
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if (foom[3].x !== 1'b1) $stop;
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//
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if (subs[0].x !== 1'b1) $stop;
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if (subs[1].x !== 1'b1) $stop;
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if (subs[2].x !== 1'b0) $stop;
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//
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if (subl[1].x !== 1'b1) $stop;
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if (subl[2].x !== 1'b1) $stop;
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if (subl[3].x !== 1'b0) $stop;
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//
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if (subm[1].x !== 1'b0) $stop;
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if (subm[2].x !== 1'b1) $stop;
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if (subm[3].x !== 1'b1) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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