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110 lines
2.5 KiB
Verilog
110 lines
2.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [15:0] out; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[15:0]),
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// Inputs
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.in (in[31:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {48'h0, out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4afe43fb79d7b71e
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module callee (input [7:0] port [7:0], output [7:0] o);
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assign o = ^{port[0], port[1], port[2], port[3],
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port[4], port[5], port[6], port[7]};
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endmodule // callee
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module Test (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in
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);
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input [31:0] in;
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output reg [15:0] out;
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wire [7:0] port [15:0];
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wire [7:0] goodport [7:0];
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always_comb begin
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port[0][7:0] = in[7:0];
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port[1][7:0] = in[16:8];
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port[2] = '0;
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port[3] = '0;
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port[4] = '0;
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port[5] = '0;
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port[6] = '0;
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port[7] = '0;
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end
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always_comb begin
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goodport[0][7:0] = in[7:0];
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goodport[1][7:0] = in[16:8];
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goodport[2] = '0;
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goodport[3] = '0;
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goodport[4] = '0;
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goodport[5] = '0;
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goodport[6] = '0;
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goodport[7] = '0;
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end
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callee good (.port(goodport), .o(out[7:0]));
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// This is a slice, unsupported by other tools, bug711
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callee bad (.port(port[7:0]), .o(out[15:8]));
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endmodule
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