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69 lines
1.6 KiB
Verilog
69 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2009 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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`ifdef VCS
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`define NO_SHORTREAL
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`endif
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`ifdef NC
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`define NO_SHORTREAL
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`endif
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`ifdef VERILATOR // Unsupported
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`define NO_SHORTREAL
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`endif
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module t (/*AUTOARG*/);
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// Note these are NOT pure.
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import "DPI-C" function int dpii_clear ();
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import "DPI-C" function int dpii_count (input int ctr);
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import "DPI-C" function bit dpii_inc0 (input int ctr);
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import "DPI-C" function bit dpii_inc1 (input int ctr);
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import "DPI-C" function bit dpii_incx (input int ctr, input bit value);
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integer i;
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integer j;
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integer k;
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bit b;
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integer errors;
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task check1(integer line, bit got, bit ex);
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if (got != ex) begin
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$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
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errors++;
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end
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endtask
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task check(integer line, int got, int ex);
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if (got != ex) begin
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$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
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errors++;
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end
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endtask
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// Test loop
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initial begin
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// bug963
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// verilator lint_off IGNOREDRETURN
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dpii_clear();
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// verilator lint_on IGNOREDRETURN
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j = 0;
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for (i=0; i<64; i++) begin
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if (i[0])
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j = 0;
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else
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j = {31'b0, dpii_inc1(0)};
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k = k + j;
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end
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$write("%x\n",k);
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check (`__LINE__, dpii_count(0), 32);
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if (|errors) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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