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82 lines
2.0 KiB
Verilog
82 lines
2.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Outputs
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q0, q1, q2, q3, q4, q5, q6a, q6b,
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// Inputs
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clk, d, rst0_n
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);
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input clk;
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input d;
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// OK -- from primary
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input rst0_n;
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output wire q0;
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Flop flop0 (.q(q0), .rst_n(rst0_n), .clk(clk), .d(d));
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// OK -- from flop
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reg rst1_n;
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always @ (posedge clk) rst1_n <= rst0_n;
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output wire q1;
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Flop flop1 (.q(q1), .rst_n(rst1_n), .clk(clk), .d(d));
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// Bad - logic
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wire rst2_bad_n = rst0_n | rst1_n;
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output wire q2;
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Flop flop2 (.q(q2), .rst_n(rst2_bad_n), .clk(clk), .d(d));
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// Bad - logic in submodule
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wire rst3_bad_n;
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Sub sub (.z(rst3_bad_n), .a(rst0_n), .b(rst1_n));
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output wire q3;
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Flop flop3 (.q(q3), .rst_n(rst3_bad_n), .clk(clk), .d(d));
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// OK - bit selection
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reg [3:0] rst4_n;
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always @ (posedge clk) rst4_n <= {4{rst0_n}};
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output wire q4;
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Flop flop4 (.q(q4), .rst_n(rst4_n[1]), .clk(clk), .d(d));
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// Bad - logic, but waived
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// verilator lint_off CDCRSTLOGIC
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wire rst5_waive_n = rst0_n & rst1_n;
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// verilator lint_on CDCRSTLOGIC
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output wire q5;
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Flop flop5 (.q(q5), .rst_n(rst5_waive_n), .clk(clk), .d(d));
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// Bad - for graph test - logic feeds two signals, three destinations
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wire rst6_bad_n = rst0_n ^ rst1_n;
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wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); // $c prevents optimization
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wire rst6b_bad_n = rst6_bad_n ^ $c1("1");
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output wire q6a;
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output wire q6b;
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Flop flop6a (.q(q6a), .rst_n(rst6a_bad_n), .clk(clk), .d(d));
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Flop flop6v (.q(q6b), .rst_n(rst6b_bad_n), .clk(clk), .d(d));
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initial begin
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$display("%%Error: Not a runnable test");
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$stop;
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end
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endmodule
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module Flop (
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input clk,
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input d,
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input rst_n,
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output q);
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) q <= 1'b0;
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else q <= d;
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end
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endmodule
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module Sub (input a, b,
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output z);
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wire z = a|b;
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endmodule
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