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92 lines
2.1 KiB
Verilog
92 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Ed Lander.
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// verilator lint_off WIDTH
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] p1;
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reg [7:0] p2;
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reg [7:0] p3;
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initial begin
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p1 = 8'h01;
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p2 = 8'h02;
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p3 = 8'h03;
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end
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parameter int param1 = 8'h11;
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parameter int param2 = 8'h12;
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parameter int param3 = 8'h13;
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targetmod i_targetmod (/*AUTOINST*/
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// Inputs
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.clk (clk));
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//Binding i_targetmod to mycheck --instantiates i_mycheck inside i_targetmod
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//param1 not over-riden (as mycheck) (=> 0x31)
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//param2 explicitly bound to targetmod value (=> 0x22)
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//param3 explicitly bound to top value (=> 0x13)
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//p1 implictly bound (.*), takes value from targetmod (=> 0x04)
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//p2 explictly bound to targetmod (=> 0x05)
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//p3 explictly bound to top (=> 0x03)
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// Alternative unsupported form is i_targetmod
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bind targetmod mycheck
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#(
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.param2(param2),
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.param3(param3)
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)
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i_mycheck (.p2(p2), .p3(p3), .*);
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endmodule
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module targetmod (input clk);
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reg [7:0] p1;
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reg [7:0] p2;
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reg [7:0] p3;
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parameter int param1 = 8'h21;
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parameter int param2 = 8'h22;
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parameter int param3 = 8'h23;
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initial begin
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p1 = 8'h04;
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p2 = 8'h05;
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p3 = 8'h06;
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end
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endmodule
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module mycheck (/*AUTOARG*/
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// Inputs
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clk, p1, p2, p3
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);
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input clk;
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input [7:0] p1;
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input [7:0] p2;
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input [7:0] p3;
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parameter int param1 = 8'h31;
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parameter int param2 = 8'h32;
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parameter int param3 = 8'h33;
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always @ (posedge clk) begin
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`checkh(param1,8'h31);
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`checkh(param2,8'h22);
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`checkh(param3,8'h23);
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`checkh(p1,8'h04);
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`checkh(p2,8'h05);
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`checkh(p3,8'h06);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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