mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
7 lines
461 B
Plaintext
7 lines
461 B
Plaintext
%Warning-WIDTH: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
|
|
: ... In instance t
|
|
10 | wire [3:0] foo = 6'h2e;
|
|
| ^
|
|
... For warning description see https://verilator.org/warn/WIDTH?v=latest
|
|
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
|