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599d23697d
This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278
41 lines
1.2 KiB
C++
41 lines
1.2 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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//
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// Copyright 2022 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#include <memory>
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#include "verilated.h"
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#include "Vt_comb_input_1.h"
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#include "Vt_comb_input_1__Syms.h"
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int main(int argc, char** argv, char** env) {
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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contextp->commandArgs(argc, argv);
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contextp->debug(0);
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srand48(5);
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const std::unique_ptr<Vt_comb_input_1> topp{new Vt_comb_input_1};
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topp->inc = 1;
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topp->clk = false;
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topp->eval();
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while (!contextp->gotFinish() && contextp->time() < 100000) {
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contextp->timeInc(5);
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if (topp->clk) topp->inc += 1;
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topp->clk = !topp->clk;
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topp->eval();
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}
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if (!contextp->gotFinish()) {
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vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish");
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}
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return 0;
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}
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