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60 lines
1.3 KiB
Systemverilog
60 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module class_tb ();
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interface class Ibase;
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pure virtual function int fn();
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endclass
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interface class Ic1 extends Ibase;
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pure virtual function int fn1();
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endclass
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interface class Ic2 extends Ibase;
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pure virtual function int fn2();
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endclass
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interface class Ic3 extends Ic1, Ic2;
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endclass
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class Cls implements Ic3;
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virtual function int fn();
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return 10;
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endfunction
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virtual function int fn1();
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return 1;
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endfunction
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virtual function int fn2();
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return 2;
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endfunction
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endclass
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initial begin
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Cls cls;
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Ibase ibase;
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Ic1 ic1;
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Ic2 ic2;
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Ic3 ic3;
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cls = new;
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if (cls.fn() != 10) $stop;
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if (cls.fn1() != 1) $stop;
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if (cls.fn2() != 2) $stop;
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ibase = cls;
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ic1 = cls;
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ic2 = cls;
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ic3 = cls;
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if (ibase.fn() != 10) $stop;
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if (ic1.fn() != 10) $stop;
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if (ic2.fn() != 10) $stop;
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if (ic3.fn() != 10) $stop;
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if (ic1.fn1() != 1) $stop;
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if (ic2.fn2() != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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