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27 lines
583 B
Systemverilog
27 lines
583 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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initial begin
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int x = 0;
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while (x < 10) begin : outer_loop
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int y = 0;
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while (y < x) begin : inner_loop
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static int a = 0;
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a++;
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y++;
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end
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x++;
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end
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if (outer_loop.inner_loop.a != 45) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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