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708abe0dd1
This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes. |
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| .. | ||
| figures | ||
| changes.rst | ||
| conf.py | ||
| connecting.rst | ||
| contributing.rst | ||
| contributors.rst | ||
| copyright.rst | ||
| deprecations.rst | ||
| environment.rst | ||
| example_cc.rst | ||
| example_common_install.rst | ||
| example_dist.rst | ||
| example_sc.rst | ||
| examples.rst | ||
| exe_sim.rst | ||
| exe_verilator_coverage.rst | ||
| exe_verilator_gantt.rst | ||
| exe_verilator_profcfuncs.rst | ||
| exe_verilator.rst | ||
| executables.rst | ||
| extensions.rst | ||
| faq.rst | ||
| files.rst | ||
| index.rst | ||
| install.rst | ||
| languages.rst | ||
| overview.rst | ||
| simulating.rst | ||
| verilating.rst | ||
| warnings.rst | ||