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42 lines
1.9 KiB
XML
42 lines
1.9 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2023"/>
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<file id="b" filename="<command-line>" language="1800-2023"/>
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<file id="c" filename="input.vc" language="1800-2023"/>
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<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2023"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_xml_flat_pub_mod.v" language="1800-2023"/>
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</module_files>
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<cells>
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<cell loc="d,11,8,11,11" name="$root" submodname="$root" hier="$root"/>
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</cells>
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<netlist>
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<module loc="d,11,8,11,11" name="$root" origName="$root" topModule="1" public="true">
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<var loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
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<var loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
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<var loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
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<topscope loc="d,11,8,11,11">
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<scope loc="d,11,8,11,11" name="TOP">
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<varscope loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
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<varscope loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
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<varscope loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
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<assignalias loc="d,11,24,11,29" dtype_id="1">
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<varref loc="d,11,24,11,29" name="i_clk" dtype_id="1"/>
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<varref loc="d,11,24,11,29" name="top.i_clk" dtype_id="1"/>
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</assignalias>
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<assignalias loc="d,7,24,7,29" dtype_id="1">
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<varref loc="d,12,7,12,8" name="top.i_clk" dtype_id="1"/>
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<varref loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1"/>
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</assignalias>
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</scope>
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</topscope>
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</module>
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<typetable loc="a,0,0,0,0">
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<basicdtype loc="d,11,18,11,23" id="1" name="logic"/>
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</typetable>
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</netlist>
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</verilator_xml>
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