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https://github.com/verilator/verilator.git
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5e1fc6e24d
This functionality used to be distributed in the removeVars pass and the final dfgToAst conversion. Instead added a new 'regularize' pass to convert DFGs into forms that can be trivially converted back to Ast, and a new 'eliminateVars' pass to remove/repalce redundant variables. This simplifies dfgToAst significantly and makes the code a bit easier to follow. The new 'regularize' pass will ensure that every sub-expression with multiple uses is assigned to a temporary (unless it's a trivial memory reference or constant), and will also eliminate or replace redundant variables. Overall it is a performance neutral change but it does enable some later improvements which required the graph to be in this form, and this also happens to be the form required for the dfgToAst conversion.
86 lines
4.4 KiB
XML
86 lines
4.4 KiB
XML
<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2023"/>
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<file id="b" filename="<command-line>" language="1800-2023"/>
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<file id="c" filename="input.vc" language="1800-2023"/>
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<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_xml_first.v" language="1800-2023"/>
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</module_files>
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<cells>
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<cell loc="d,7,8,7,9" name="t" submodname="t" hier="t">
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<cell loc="d,20,4,20,9" name="cell1" submodname="mod1__W4" hier="t.cell1"/>
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<cell loc="d,25,6,25,11" name="cell2" submodname="mod2" hier="t.cell2"/>
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</cell>
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</cells>
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<netlist>
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<module loc="d,7,8,7,9" name="t" origName="t" topModule="1">
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<var loc="d,15,22,15,23" name="q" dtype_id="1" dir="output" pinIndex="1" vartype="logic" origName="q"/>
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<var loc="d,13,10,13,13" name="clk" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="clk"/>
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<var loc="d,14,16,14,17" name="d" dtype_id="1" dir="input" pinIndex="3" vartype="logic" origName="d"/>
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<var loc="d,17,22,17,29" name="between" dtype_id="1" vartype="logic" origName="between"/>
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<instance loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
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<port loc="d,20,12,20,13" name="q" direction="out" portIndex="1">
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<varref loc="d,20,14,20,21" name="between" dtype_id="1"/>
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</port>
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<port loc="d,21,12,21,15" name="clk" direction="in" portIndex="2">
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<varref loc="d,21,42,21,45" name="clk" dtype_id="2"/>
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</port>
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<port loc="d,22,12,22,13" name="d" direction="in" portIndex="3">
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<varref loc="d,22,42,22,43" name="d" dtype_id="1"/>
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</port>
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</instance>
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<instance loc="d,25,6,25,11" name="cell2" defName="mod2" origName="cell2">
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<port loc="d,25,14,25,15" name="d" direction="in" portIndex="1">
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<varref loc="d,25,16,25,23" name="between" dtype_id="1"/>
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</port>
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<port loc="d,26,14,26,15" name="q" direction="out" portIndex="2">
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<varref loc="d,26,42,26,43" name="q" dtype_id="1"/>
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</port>
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<port loc="d,27,14,27,17" name="clk" direction="in" portIndex="3">
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<varref loc="d,27,42,27,45" name="clk" dtype_id="2"/>
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</port>
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</instance>
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</module>
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<module loc="d,46,8,46,12" name="mod2" origName="mod2">
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<var loc="d,48,10,48,13" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
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<var loc="d,49,16,49,17" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
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<var loc="d,50,22,50,23" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
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<contassign loc="d,53,13,53,14" dtype_id="1">
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<varref loc="d,49,16,49,17" name="d" dtype_id="1"/>
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<varref loc="d,53,13,53,14" name="q" dtype_id="1"/>
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</contassign>
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</module>
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<module loc="d,31,8,31,12" name="mod1__W4" origName="mod1">
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<var loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
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<const loc="d,19,18,19,19" name="32'sh4" dtype_id="3"/>
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</var>
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<var loc="d,34,24,34,27" name="clk" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
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<var loc="d,35,30,35,31" name="d" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="d"/>
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<var loc="d,36,30,36,31" name="q" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="q"/>
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<var loc="d,39,15,39,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
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<const loc="d,39,25,39,26" name="32'sh1" dtype_id="3"/>
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</var>
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<always loc="d,41,4,41,10">
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<sentree loc="d,41,11,41,12">
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<senitem loc="d,41,13,41,20" edgeType="POS">
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<varref loc="d,41,21,41,24" name="clk" dtype_id="2"/>
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</senitem>
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</sentree>
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<assigndly loc="d,42,8,42,10" dtype_id="1">
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<varref loc="d,42,11,42,12" name="d" dtype_id="1"/>
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<varref loc="d,42,6,42,7" name="q" dtype_id="1"/>
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</assigndly>
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</always>
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</module>
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<typetable loc="a,0,0,0,0">
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<basicdtype loc="d,34,24,34,27" id="2" name="logic"/>
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<basicdtype loc="d,15,16,15,17" id="1" name="logic" left="3" right="0"/>
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<basicdtype loc="d,19,18,19,19" id="3" name="logic" left="31" right="0" signed="true"/>
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</typetable>
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</netlist>
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</verilator_xml>
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