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20 lines
558 B
Systemverilog
20 lines
558 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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initial begin
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// This test is separate from t_wait.v because we needed a process with
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// just one wait of a non-zero to see a bug where GCC gave "return value
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// not used"
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// verilator lint_off WAITCONST
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wait (1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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