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61 lines
1.8 KiB
Perl
Executable File
61 lines
1.8 KiB
Perl
Executable File
#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2023 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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use IO::File;
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scenarios(vlt => 1);
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$Self->{sanitize} = 0; # GCC takes too long otherwise
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sub gen {
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my $filename = shift;
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my $n = shift;
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my $fh = IO::File->new(">$filename");
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$fh->print("// Generated by t_vthread.pl\n");
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$fh->print("module genmod #(int val = 0)(clk, o);\n");
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$fh->print(" input clk;\n");
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$fh->print(" output int o;\n");
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$fh->print(" always @ (posedge clk) begin\n");
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$fh->print(" o <= val;\n");
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$fh->print(" end\n");
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$fh->print("endmodule\n");
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$fh->print("module t (clk, o);\n");
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$fh->print(" input clk;\n");
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$fh->print(" output int o;\n");
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for (my $i = 0; $i < ($n + 1); ++$i) {
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$fh->print(" int r$i;\n");
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$fh->print(" genmod #(.val($i)) rm$i (.clk(clk), .o(r$i));\n");
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}
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$fh->print(" always @ (posedge clk) begin\n");
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$fh->print(" o <= r$n;\n");
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$fh->print(' $write("*-* All Finished *-*\n");', "\n");
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$fh->print(' $finish;', "\n");
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$fh->print(" end\n");
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$fh->print("endmodule\n");
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}
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top_filename("$Self->{obj_dir}/t_vthread.v");
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gen($Self->{top_filename}, 6000);
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compile(
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# use --trace to generate trace files that can be parallelized
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verilator_flags2=>["--stats --trace --verilate-jobs 2"],
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);
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execute(
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check_finished => 1,
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);
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file_grep($Self->{stats}, qr/Verilate jobs: 2/);
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ok(1);
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1;
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