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73 lines
1.6 KiB
Systemverilog
73 lines
1.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class cls;
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static task automatic tsk1;
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integer task_assign = 1;
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if (task_assign != 1) $stop;
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task_assign = 2;
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if (task_assign != 2) $stop;
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endtask
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static task tsk2;
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integer task_assign = 1;
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if (task_assign != 1) $stop;
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task_assign = 2;
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if (task_assign != 2) $stop;
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endtask
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endclass
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module t;
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integer top;
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integer top_assign=1;
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task automatic tsk;
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integer task_assign = 1;
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if (task_assign != 1) $stop;
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task_assign = 2;
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if (task_assign != 2) $stop;
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endtask
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initial begin
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begin : a
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integer lower;
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integer lower_assign=1;
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lower = 1;
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top = 1;
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if (lower != 1) $stop;
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if (lower_assign != 1) $stop;
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begin : aa
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integer lev2;
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lev2 = 1;
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lower = 2;
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lower_assign = 2;
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top = 2;
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end
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if (lower != 2) $stop;
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if (lower_assign != 2) $stop;
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end
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begin : b
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integer lower;
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lower = 1;
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top = 2;
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begin : empty
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begin : empty
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end
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end
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end
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// Repeat task calls to ensure we reinit the initial value
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tsk;
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tsk;
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cls::tsk1();
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cls::tsk1();
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cls::tsk2();
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cls::tsk2();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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