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83 lines
2.1 KiB
Systemverilog
83 lines
2.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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\escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done ,
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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output \escaped_normal ;
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wire \escaped_normal = cyc[0];
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output double__underscore ;
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wire double__underscore = cyc[0];
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wire underscore_at_the_end_ = cyc[0];
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wire double__underscore_at_the_end__ = cyc[0];
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// Only underscores, ignored in trace
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wire _ = cyc[0];
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wire __ = cyc[0];
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wire ___ = cyc[0];
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wire ____ = cyc[0];
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// C doesn't allow leading non-alpha, so must escape
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output \9num ;
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wire \9num = cyc[0];
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output \bra[ket]slash/dash-colon:9backslash\done ;
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wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0];
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wire \wire = cyc[0];
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wire \check_alias = cyc[0];
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wire \check:alias = cyc[0];
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wire \check;alias = !cyc[0];
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// These are *different entities*, bug83
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wire [31:0] \a0.cyc = ~a0.cyc;
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wire [31:0] \other.cyc = ~a0.cyc;
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sub a0 (.cyc(cyc));
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sub \mod.with_dot (.cyc(cyc));
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (escaped_normal != cyc[0]) $stop;
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if (\escaped_normal != cyc[0]) $stop;
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if (underscore_at_the_end_ != cyc[0]) $stop;
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if (double__underscore_at_the_end__ != cyc[0]) $stop;
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if (_ != cyc[0]) $stop;
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if (__ != cyc[0]) $stop;
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if (___ != cyc[0]) $stop;
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if (____ != cyc[0]) $stop;
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if (\9num != cyc[0]) $stop;
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if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop;
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if (\wire != cyc[0]) $stop;
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if (\check_alias != cyc[0]) $stop;
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if (\check:alias != cyc[0]) $stop;
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if (\check;alias != !cyc[0]) $stop;
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if (\a0.cyc != ~cyc) $stop;
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if (\other.cyc != ~cyc) $stop;
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module sub (
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input [31:0] cyc
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);
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endmodule
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