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23 lines
428 B
Systemverilog
23 lines
428 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Illegal with ANSI Verilog 2001 style ports
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module t
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(
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output bad_o_w,
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output bad_o_r);
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wire bad_o_w;
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reg bad_o_r;
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wire bad_w_r;
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reg bad_w_r;
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wire bad_r_w;
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reg bad_r_w;
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endmodule
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