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50 lines
1.4 KiB
Systemverilog
50 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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typedef string array_of_string_t[];
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typedef struct {
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string positive;
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string negative;
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} filter_expression_parts_t;
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function automatic array_of_string_t split_by_char(string c, string s);
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string parts[$];
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int last_char_position = -1;
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for (int i = 0; i < s.len(); i++) begin
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if (i == s.len()-1)
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parts.push_back(s.substr(last_char_position+1, i));
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if (string'(s[i]) == c) begin
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parts.push_back(s.substr(last_char_position+1, i-1));
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last_char_position = i;
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end
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end
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$display("%p", parts);
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return parts;
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endfunction
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function filter_expression_parts_t get_filter_expression_parts(string raw_filter);
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string parts[];
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parts = split_by_char("-", raw_filter);
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return '{ parts[0], parts[1] };
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endfunction
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initial begin
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string raw_filter = "parta-partb";
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filter_expression_parts_t parts = get_filter_expression_parts(raw_filter);
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$display("%p", parts);
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if (parts.positive != "parta") $stop;
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if (parts.negative != "partb") $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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