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35 lines
687 B
Systemverilog
35 lines
687 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2023 by Yutetsu TAKATSUKASA.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic [7:0] s0;
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logic [7:0] s1[1:2];
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logic [7:0] s2[1:4];
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logic [7:0] s3[2][2];
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typedef int AI3[1:3];
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AI3 A3;
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logic [31:0] A9_logic[1:9];
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initial begin
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// RHS has too many elements.
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s1 = {s0, s2};
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s2 = {s1, s0, s0, s0};
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// Incompatible type
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s2 = {s0, s3};
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A9_logic = {A3, 4, 5, A3, 6};
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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