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28 lines
557 B
Systemverilog
28 lines
557 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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bit x;
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} u_struct_t;
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module u_mh (inout u_struct_t u_i, inout u_struct_t u_o);
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assign u_o.x = u_i.x;
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endmodule
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module t;
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u_struct_t u_i, u_o;
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u_mh u_mh(u_i, u_o);
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initial begin
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u_i.x = 1;
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#1;
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if (u_o.x != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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