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d20f22beb1
* Tests: Add a test to reproduce #3399 * Fix #3399. When reading an inout port in a module, it should refer the original inout port, not the generated MODTEMP.
113 lines
3.6 KiB
Systemverilog
113 lines
3.6 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Lane Brooks.
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// SPDX-License-Identifier: CC0-1.0
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module top (input A, input B, input SEL, input clk, output Y1, output Y2, output Z, output done);
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io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1));
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pass io2(.A(B), .OE(!SEL), .Z(Z), .Y(Y2));
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assign Z = 1'bz;
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pad_checker u_pad_checker(.clk(clk), .done(done));
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endmodule
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module pass (input A, input OE, inout Z, output Y);
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io_noinline io(.A(A), .OE(OE), .Z(Z), .Y(Y));
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assign Z = 1'bz;
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endmodule
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module io (input A, input OE, inout Z, output Y);
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assign Z = (OE) ? A : 1'bz;
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assign Y = Z;
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assign Z = 1'bz;
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endmodule
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module io_noinline (input A, input OE, inout Z, output Y);
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/*verilator no_inline_module*/
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assign Z = (OE) ? A : 1'bz;
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assign Y = Z;
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assign Z = 1'bz;
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endmodule
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module pad_checker(input wire clk, output wire done);
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wire tri_pad;
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reg [1:0] ie = '0;
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reg [1:0] oe = '0;
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reg [1:0] in = '0;
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wire out_0, out_1;
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pad u_pad0(.pad(tri_pad), .ie(ie[0]), .oe(oe[0]), .to_pad(in[0]), .from_pad(out_0));
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pad u_pad1(.pad(tri_pad), .ie(ie[1]), .oe(oe[1]), .to_pad(in[1]), .from_pad(out_1));
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wire bin_pad_in_0, bin_pad_in_1;
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wire bin_pad_01, bin_pad_10;
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wire bin_pad_en_01, bin_pad_en_10;
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wire bin_from_pad_out_0, bin_from_pad_out_1;
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wire bin_from_pad_en_0, bin_from_pad_en_1;
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// Expectation model that simulates how Verilator solves tri-state
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pad_binary u_pad_bin_0(.pad_in(bin_pad_in_0),
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.pad_out(bin_pad_01),
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.pad_en(bin_pad_en_01),
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.ie(ie[0]), .oe(oe[0]),
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.to_pad(in[0]),
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.from_pad_out(bin_from_pad_out_0),
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.from_pad_en(bin_from_pad_en_0));
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pad_binary u_pad_bin_1(.pad_in(bin_pad_in_1),
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.pad_out(bin_pad_10),
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.pad_en(bin_pad_en_10),
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.ie(ie[1]),
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.oe(oe[1]),
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.to_pad(in[1]),
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.from_pad_out(bin_from_pad_out_1),
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.from_pad_en(bin_from_pad_en_1));
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assign bin_pad_in_0 = (bin_pad_en_10 & bin_pad_10) | (bin_pad_en_01 & bin_pad_01);
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assign bin_pad_in_1 = (bin_pad_en_01 & bin_pad_01) | (bin_pad_en_10 & bin_pad_10);
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logic done_reg = 0;
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assign done = done_reg;
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always @(posedge clk) begin
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if ({ie, oe, in} == 6'b111111) begin
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done_reg <= 1'b1;
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end else begin
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if (out_0 != bin_from_pad_out_0) begin
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$display("ie:%b oe:%b in:%b out0 act:%b exp:%b", ie[0], oe[0], in[0], out_0, bin_from_pad_out_0);
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$stop;
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end
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if (out_1 != bin_from_pad_out_1) begin
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$display("ie:%b oe:%b in:%b out1 act:%b exp:%b", ie[1], oe[1], in[1], out_1, bin_from_pad_out_1);
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$stop;
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end
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// Let's try all combination
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{ie, oe, in} <= {ie, oe, in} + 1;
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end
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end
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endmodule
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module pad(inout wire pad, input wire ie, input wire oe, input wire to_pad, output wire from_pad);
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assign pad = oe ? to_pad : 1'bz;
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assign from_pad = ie ? pad : 1'bz;
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endmodule
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module pad_binary(input wire pad_in,
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output wire pad_out,
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output wire pad_en,
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input wire ie,
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input wire oe,
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input wire to_pad,
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output from_pad_out,
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output wire from_pad_en);
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assign pad_out = oe & to_pad;
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assign pad_en = oe;
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assign from_pad_out = ie & ((oe & to_pad) | pad_in);
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assign from_pad_en = ie;
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endmodule
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