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28 lines
608 B
Systemverilog
28 lines
608 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef enum logic [1:0] {VAL_A, VAL_B, VAL_C, VAL_D} state_t;
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interface MyIntf;
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state_t state;
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endinterface
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module t (clk);
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input clk;
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MyIntf #() sink ();
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state_t v_enumed;
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typedef enum logic [1:0] {VAL_X, VAL_Y, VAL_Z} other_state_t;
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other_state_t v_other_enumed;
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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