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28 lines
608 B
Systemverilog
28 lines
608 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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reg [7:0] vec1 [3:0], vec2 [3:0];
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always
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for (int i = 0; i < 4; i++)
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vec2[i] = vec1[i];
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initial begin
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#1 vec1[0] = 8'h0f;
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#1 vec1[1] = 8'h04;
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#1 vec1[2] = 8'h0e;
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#1 vec1[3] = 8'h0a;
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#1
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for (int i = 0; i < 4; i++)
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if (vec1[i] != vec2[i]) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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