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76 lines
1.7 KiB
Systemverilog
76 lines
1.7 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic clk1 = 0;
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assign #3 clk1 = ~clk1;
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logic clk2 = 0;
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assign #11 clk2 = ~clk2;
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logic flag = 0;
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int a1 = 0;
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int b1 = 0;
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int c1 = 0;
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always @(posedge clk1) begin
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if (flag) #4 a1 = a1 + 1;
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else @(posedge clk2) b1 = b1 + 1;
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c1 = c1 + 1;
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flag = ~flag;
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end
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int a2 = 0;
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always_comb begin
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// verilator lint_off MULTIDRIVEN
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a2 = a1 << 1;
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// verilator lint_on MULTIDRIVEN
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`ifdef TEST_VERBOSE
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$display("[%0t] a2 = %0d", $time, a2);
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`endif
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end
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int b2 = 0;
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always_comb begin
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// verilator lint_off MULTIDRIVEN
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b2 = b1 << 2;
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// verilator lint_on MULTIDRIVEN
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`ifdef TEST_VERBOSE
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$display("[%0t] b2 = %0d", $time, b2);
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`endif
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end
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int c2 = 0;
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always_comb begin
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// verilator lint_off MULTIDRIVEN
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c2 = c1 << 3;
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// verilator lint_on MULTIDRIVEN
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`ifdef TEST_VERBOSE
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$display("[%0t] c2 = %0d", $time, c2);
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`endif
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end
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always @(posedge clk1) begin
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#1 if (c2 != c1 << 3) $stop;
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#5 if (a2 != a1 << 1) $stop;
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end
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always @(posedge clk2) #1 if (b2 != b1 << 2) $stop;
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initial #78 begin
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`ifdef TEST_VERBOSE
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$display("a1=%0d, b1=%0d, c1=%0d, a2=%0d, b2=%0d, c2=%0d", a1, b1, c1, a2, b2, c2);
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`endif
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if (a1 != 3) $stop;
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if (b1 != 4) $stop;
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if (c1 != a1 + b1) $stop;
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if (a2 != a1 << 1) $stop;
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if (b2 != b1 << 2) $stop;
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if (c2 != c1 << 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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