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42 lines
950 B
Systemverilog
42 lines
950 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns / 1ns
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static int counts[10];
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class Foo;
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static task do_something();
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for (int i = 0; i < 10; i++) begin // Should create a dynamic scope for `i`
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int ci = i; // Should create another dynamic scope for `ci`, local to the begin block
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fork begin
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#10;
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$display("ci: %d, i: %d", ci, i);
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if (i != 10)
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$stop;
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if (counts[ci-1]++ > 0)
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$stop;
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end join_none
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ci++;
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end
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endtask
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endclass
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module t();
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initial begin
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int desired_counts[10];
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counts = '{10{0}};
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desired_counts = '{10{1}};
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Foo::do_something();
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#20;
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if (counts != desired_counts)
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$stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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