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31 lines
592 B
Systemverilog
31 lines
592 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define DELAY 10
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class Foo;
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task wait_dynamically();
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#`DELAY;
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endtask
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static task wait_statically();
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#`DELAY;
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endtask
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endclass
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module t;
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Foo foo = new;
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initial begin
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foo.wait_dynamically();
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if ($time != `DELAY) $stop;
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Foo::wait_statically();
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if ($time != 2*`DELAY) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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