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23 lines
731 B
Systemverilog
23 lines
731 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define STRINGIFY(x) `"x`"
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module t();
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reg [7:0] rom [4];
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initial begin
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$readmemh({`STRINGIFY(`TEST_OBJ_DIR), "/dat.mem"}, rom);
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`checkh(rom[0], 8'h1);
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`checkh(rom[1], 8'h10);
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`checkh(rom[2], 8'h20);
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`checkh(rom[3], 8'h30);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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