verilator/test_regress/t/t_sys_readmem_4state.mem
2024-05-21 17:27:32 -04:00

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// DESCRIPTION: Verilator: Verilog Test data file
//
// Copyright 2024 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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