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44 lines
1.1 KiB
Systemverilog
44 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t;
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int i;
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int v;
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string s;
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reg [100*8:1] letterl;
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initial begin
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// Display formatting
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$fwrite(0, "Never printed, file closed\n");
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i = $feof(0);
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if (i == 0) $stop;
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$fflush(0);
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$fclose(0);
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i = $ferror(0, letterl);
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i = $fgetc(0);
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`checkd(i, -1);
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i = $ungetc(0, 0);
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`checkd(i, -1);
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i = $fgets(letterl, 0);
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`checkd(i, 0);
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i = $fscanf(0, "%x", v);
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`checkd(i, -1);
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i = $ftell(0);
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`checkd(i, -1);
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i = $rewind(0);
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`checkd(i, -1);
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i = $fseek(0, 10, 0);
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`checkd(i, -1);
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$write("*-* All Finished *-*\n");
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$finish(0); // Test arguments to finish
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end
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endmodule
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