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37 lines
1.0 KiB
Systemverilog
37 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t;
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integer infile, outfile;
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integer count, a;
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initial begin
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infile = $fopen("t/t_sys_file_scan_input.dat", "r");
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outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w");
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count = 1234;
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`ifdef TEST_VERBOSE
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$display("-count == %0d, infile %d, outfile %d", count, infile, outfile);
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`endif
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count = $fscanf(infile, "%d\n", a);
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`ifdef TEST_VERBOSE
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// Ifdefing this out gave bug248
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$display("-count == %0d, infile %d, outfile %d", count, infile, outfile);
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`endif
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if (count == 0) $stop;
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$fwrite(outfile, "# a\n");
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$fwrite(outfile, "%d\n", a);
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$fclose(infile);
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$fclose(outfile);
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$write("*-* All Finished *-*\n");
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$finish(0); // Test arguments to finish
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end
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endmodule
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