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34 lines
842 B
Systemverilog
34 lines
842 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t;
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integer f;
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integer i;
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integer j;
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initial begin
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f = $fopen("/does-not-exist", "r");
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`checkd(f, 0);
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i = $fscanf(f, "check %d", j);
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`checkd(i, -1);
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i = $fgetc(f);
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`checkd(i, -1);
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i = $ftell(f);
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`checkd(i, -1);
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i = $rewind(f);
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`checkd(i, -1);
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i = $fseek(f, 0, 0);
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`checkd(i, -1);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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