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30 lines
569 B
Systemverilog
30 lines
569 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct {
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logic [4:0] w5;
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} Data_t;
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module t;
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reg en;
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reg [7:0] r_id;
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Data_t ts;
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initial begin
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en = 1;
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r_id = 42;
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ts = '{w5: en ? r_id[4:0] : 5'b0};
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$display("ts.w5 = %h", ts.w5);
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if ($c32(ts.w5) != 5'h0a) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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