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68 lines
1.4 KiB
Systemverilog
68 lines
1.4 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009-2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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class Cls;
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typedef struct {
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string m_strg;
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} underclass_t;
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underclass_t m_cstr;
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function underclass_t get_cstr();
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m_cstr.m_strg = "foo";
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return m_cstr;
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endfunction
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endclass
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module x;
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typedef struct {
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int a, b;
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logic [3:0] c;
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} embedded_t;
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typedef struct {
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embedded_t b;
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embedded_t tab [3:0];
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} notembedded_t;
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typedef struct {
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logic [15:0] m_i;
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string m_s;
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} istr_t;
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notembedded_t p;
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embedded_t t [1:0];
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istr_t istr;
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string s;
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Cls c;
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initial begin
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t[1].a = 2;
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p.b.a = 1;
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if (t[1].a != 2) $stop;
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if (p.b.a != 1) $stop;
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istr.m_i = 12;
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istr.m_s = "str1";
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s = $sformatf("%p", istr);
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`checks(s, "'{m_i:'hc, m_s:\"str1\"}");
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istr = '{m_i: '1, m_s: "str2"};
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s = $sformatf("%p", istr);
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`checks(s, "'{m_i:'hffff, m_s:\"str2\"}");
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c = new;
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s = c.get_cstr().m_strg;
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`checks(s, "foo");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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