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58 lines
1.3 KiB
Systemverilog
58 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class uvm_policy;
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typedef enum {
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NEVER,
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STARTED,
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FINISHED
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} recursion_state_e;
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endclass
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typedef enum {
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UVM_DEFAULT_POLICY = 0,
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UVM_DEEP = (1<<16),
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UVM_SHALLOW = (1<<17),
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UVM_REFERENCE = (1<<18)
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} uvm_recursion_policy_enum;
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class Cls;
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typedef struct {
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uvm_policy::recursion_state_e state;
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bit ret_val;
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} state_info_t;
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state_info_t m_recur_states/*[uvm_object][uvm_object]*/[uvm_recursion_policy_enum];
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function uvm_recursion_policy_enum get_recursion_policy();
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return UVM_DEEP;
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endfunction
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function bit get_ret_val();
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return $c(1);
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endfunction
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function void test();
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bit ret_val;
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ret_val = $c1(1);
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// See issue #4568
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m_recur_states[get_recursion_policy()] = '{uvm_policy::FINISHED, ret_val};
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endfunction
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endclass
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module t;
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initial begin
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Cls c;
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c = new;
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$display("%p", c);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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