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46 lines
1.2 KiB
Systemverilog
46 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish;
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// on success, or $stop.
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//
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// The code as shown applies a random vector to the Test
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// module, then calculates a CRC on the Test module's outputs.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here, otherwise:**
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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string s, s2;
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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s = {s2, {cyc{"*"}}};
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if (cyc != s.len()) $stop;
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if (cyc == 0 && s != "") $stop;
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if (cyc == 1 && s != "*") $stop;
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if (cyc == 2 && s != "**") $stop;
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if (cyc == 3 && s != "***") $stop;
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if (cyc == 4 && s != "****") $stop;
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if (cyc == 5 && s != "*****") $stop;
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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