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56 lines
1.8 KiB
Systemverilog
56 lines
1.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t (/*AUTOARG*/);
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initial begin
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logic [7:0] src_1 = 8'b1010_0011; // 8 bits wide source
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logic [1:0] dst_1 [3]; // 6 bits wide target
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logic [1:0] exp_1 [3]; // 6 bits wide target
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logic [1:0] src_2 [3] = '{2'b10, 2'b10, 2'b10}; // 6 bits wide source
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logic [7:0] dst_2; // 8 bits wide target
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logic [7:0] exp_2; // 8 bits wide target
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string expv;
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string gotv;
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// unpack as target, StreamR
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{>>{dst_1}} = src_1;
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exp_1 = '{2'b10, 2'b10, 2'b00};
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expv = $sformatf("%p", exp_1);
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gotv = $sformatf("%p", dst_1);
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`checks(gotv, expv);
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// unpack as target, StreamL
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{<<{dst_1}} = src_1;
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exp_1 = '{2'b00, 2'b01, 2'b01};
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expv = $sformatf("%p", exp_1);
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gotv = $sformatf("%p", dst_1);
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`checks(gotv, expv);
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// unpack as source, StreamR
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dst_2 = {>>{src_2}};
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exp_2 = 8'b10101000;
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expv = $sformatf("%p", exp_2);
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gotv = $sformatf("%p", dst_2);
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`checks(gotv, expv);
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// unpack as source, StreamL
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dst_2 = {<<{src_2}};
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exp_2 = 8'b01010100;
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expv = $sformatf("%p", exp_2);
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gotv = $sformatf("%p", dst_2);
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`checks(gotv, expv);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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