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25 lines
517 B
Systemverilog
25 lines
517 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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parameter int ZERO = 0;
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initial begin
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bit [31:0] val = '1;
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int left = 4;
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int part = val[left +: ZERO];
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$display(part);
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part = val[left -: ZERO];
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$display(part);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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