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43 lines
812 B
Systemverilog
43 lines
812 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Base;
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pure constraint pur;
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endclass
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class Packet extends Base;
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rand int header;
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rand int length;
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constraint pur { length == 3; }
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extern constraint ex;
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endclass
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constraint Packet::ex { header == 2; }
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module t (/*AUTOARG*/);
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Packet p;
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initial begin
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int v;
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v = p.randomize();
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if (v != 1) $stop;
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if (p.header != 2) $stop;
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if (p.length != 3) $stop;
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v = p.randomize(1);
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if (v != 1) $stop;
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if (p.header != 2) $stop;
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if (p.length != 3) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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