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135 lines
3.2 KiB
Systemverilog
135 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class ClsNarrow #(parameter int WIDTH);
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randc bit [WIDTH-1:0] m_var;
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function void test;
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automatic int i;
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automatic int count[2**WIDTH];
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automatic int maxcount;
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automatic bit bad;
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automatic int randomize_result;
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$display("Test %m");
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for (int trial = 0; trial < 10; ++trial) begin
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for (i = 0; i < (2 ** WIDTH); ++i) begin
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randomize_result = randomize();
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if (randomize_result !== 1) $stop;
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`ifdef TEST_VERBOSE
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$display("w%0d i=%0d m_var=%x", WIDTH, i, m_var);
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`endif
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++count[m_var];
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end
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end
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maxcount = count[0];
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bad = '0;
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`ifndef TEST_IGNORE_RANDC
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for (i = 0; i < (2 ** WIDTH); ++i) begin
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if (maxcount != count[i]) bad = '1;
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end
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`endif
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if (bad) begin
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$display("%%Error: count mismatch");
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for (i = 0; i < (2 ** WIDTH); ++i) begin
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$display("w%0d entry[%0d]=%0d", WIDTH, i, count[i]);
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end
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$stop;
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end
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endfunction
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endclass
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class ClsWide #(parameter int WIDTH);
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randc bit [WIDTH-1:0] m_var;
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function void test;
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automatic bit [WIDTH-1:0] last;
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automatic int randomize_result;
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$display("Test %m");
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for (int i = 0; i < 100; ++i) begin
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randomize_result = randomize();
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if (randomize_result !== 1) $stop;
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`ifdef TEST_VERBOSE
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$display("ww%0d i=%0d m_var=%x", WIDTH, i, m_var);
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`endif
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if (i != 0) begin
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`ifndef TEST_IGNORE_RANDC
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if (m_var == last) $stop;
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`endif
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end
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last = m_var;
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end
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endfunction
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endclass
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class ClsEnum;
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typedef enum bit [3:0] {
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TWO = 2,
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FIVE = 5,
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SIX = 6
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} enum_t;
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randc enum_t m_var;
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function void test;
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automatic enum_t last;
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automatic int randomize_result;
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$display("Test %m");
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for (int trial = 0; trial < 10; ++trial) begin
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for (int i = 0; i < 3; ++i) begin
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randomize_result = randomize();
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if (randomize_result !== 1) $stop;
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`ifdef TEST_VERBOSE
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$display("we i=%0d m_var=%x", i, m_var);
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`endif
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if (m_var != TWO && m_var != FIVE && m_var != SIX) $stop;
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if (i != 0) begin
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`ifndef TEST_IGNORE_RANDC
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if (m_var == last) $stop;
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`endif
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end
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last = m_var;
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end
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end
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endfunction
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endclass
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module t (/*AUTOARG*/);
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ClsNarrow #(1) c1; // Degenerate case
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ClsNarrow #(2) c2;
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ClsNarrow #(3) c3;
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ClsNarrow #(3) c3b; // Need to have two of same size to cover dtype dedup code
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ClsNarrow #(9) c9;
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ClsWide #(31) c31;
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ClsWide #(32) c32;
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ClsEnum ce;
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initial begin
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c1 = new;
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c1.test();
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c2 = new;
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c2.test();
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c3 = new;
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c3.test();
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c3b = new;
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c3b.test();
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c9 = new;
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c9.test();
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c31 = new;
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c31.test();
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c32 = new;
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c32.test();
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ce = new;
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ce.test();
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$write("*-* All Finished *-*\n");
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$finish();
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end
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endmodule
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