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47 lines
1.5 KiB
Systemverilog
47 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Methods defined by IEEE:
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// class process;
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// enum state { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED }; // UVM uses KILLED, FINISHED
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// static function process self();
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// function state status();
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// function void kill();
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// task await(); // Warn as unsupported (no UVM library use)
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// function void suspend(); // Warn as unsupported (no UVM library use)
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// function void resume(); // Warn as unsupported (no UVM library use)
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// function void srandom( int seed ); // Operate on all proceses for now?
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// function string get_randstate(); // Operate on all proceses for now?
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// function void set_randstate( string state ); // Operate on all proceses for now?
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// endclass
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module t(/*AUTOARG*/);
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process p;
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initial begin
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if (p != null) $stop;
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p = process::self();
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if (p.status() != process::RUNNING) $stop;
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if (p.status() == process::WAITING) $stop;
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if (p.status() == process::SUSPENDED) $stop;
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if (p.status() == process::KILLED) $stop;
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if (p.status() == process::FINISHED) $stop;
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if (0) p.kill();
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if (0) p.await();
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if (0) p.suspend();
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if (0) p.resume();
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// See also t_urandom.pl
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p.srandom(0);
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p.set_randstate(p.get_randstate());
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$display("%p", p);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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