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36 lines
1.1 KiB
Systemverilog
36 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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module t(/*AUTOARG*/);
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integer seed;
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integer r;
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initial begin
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// Illegal values
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r = $dist_chi_square(seed, 0);
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if (r != 0 && !$isunknown(r)) $stop;
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r = $dist_erlang(seed, 0, 0);
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if (r != 0 && !$isunknown(r)) $stop;
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r = $dist_exponential(seed, 0);
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if (r != 0 && !$isunknown(r)) $stop;
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// r =$dist_exponential(seed, mean); // Always valid
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r = $dist_poisson(seed, 0);
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if (r != 0 && !$isunknown(r)) $stop;
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r = $dist_t(seed, 0);
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if (r != 0 && !$isunknown(r)) $stop;
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r = $dist_uniform(seed, 10, 0);
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if (r != 10 && !$isunknown(r)) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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