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38 lines
652 B
Systemverilog
38 lines
652 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`begin_keywords "1800-2023"
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`define ONE
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`undef ZERO
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`elsif ( ONE ) // BAD: elsif without if
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`endif
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`ifdef ( ) // BAD: Missing value
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`endif
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`ifdef ( && ZERO) // BAD: Expr
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`endif
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`ifdef ( ZERO && ) // BAD: Expr
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`endif
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`ifdef ( 1 ) // BAD: Constant
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`endif
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`ifdef ( ONE & ZERO) // BAD: Operator
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`endif
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`ifdef ( % ) // BAD: % is syntax error
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`endif
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`ifdef ) // BAD: ) without (
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`endif
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`ifdef ( ONE // BAD: Missing paren
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`endif
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