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118 lines
1.9 KiB
Systemverilog
118 lines
1.9 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`begin_keywords "1800-2023"
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`define ONE
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`undef ZERO
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`ifdef ( ONE )
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"ok ( ONE )"
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`endif
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// Test no spaces around ()
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`ifdef (ZERO)
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`error "( ZERO )"
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`endif
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`ifndef ( ! ONE )
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"ok ( ! ONE )"
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`endif
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// Test no spaces around ()
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`ifndef (!ZERO)
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`error "( ! ZERO )"
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`endif
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`ifdef ( ! ZERO )
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"ok ( ! ZERO )"
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`endif
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`ifdef ( ! ONE )
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`error "( ! ONE )"
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`endif
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`ifdef ( ZERO || ZERO || ONE )
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"ok ( ZERO || ZERO || ONE )"
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`endif
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`ifdef ( ZERO || ZERO || ZERO )
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`error "( ZERO || ZERO || ZERO )"
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`endif
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`ifdef ( ONE && ONE && ONE )
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"ok ( ONE && ONE && ONE )"
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`endif
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`ifdef ( ONE && ONE && ZERO )
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`error "( ONE && ONE && ZERO )"
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`endif
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// Precedence of && is under ||
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`ifdef ( ZERO && ZERO || ONE )
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"ok ( ZERO && ZERO || ONE )"
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`endif
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`ifdef ( ONE || ZERO && ZERO )
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"ok ( ONE || ZERO && ZERO )"
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`endif
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`ifdef ZERO
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`elsif ( ONE && !( ZERO && ONE ) )
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"ok ( ONE && !( ZERO && ONE ) )"
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`endif
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`ifdef ( ZERO -> ZERO)
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"ok ( ZERO -> ZERO)"
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`endif
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// Text extra newlines
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`ifdef ( ZERO
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->
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ONE)
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"ok ( ZERO -> ONE)"
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`endif
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// Text comments
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`ifdef ( ZERO // Zero
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-> // Operator
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ONE) // One
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"ok ( ZERO -> ONE)"
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`endif
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`ifdef ( /*val*/ ZERO
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/*op*/ ->
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/*val*/ ONE)
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"ok ( ZERO -> ONE)"
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`endif
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`ifndef ( ONE -> ZERO)
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"ok ( ONE -> ZERO)"
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`endif
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`ifdef ( ONE -> ONE)
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"ok ( ONE -> ONE)"
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`endif
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`ifdef ( ZERO <-> ZERO)
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"ok ( ZERO <-> ZERO)"
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`endif
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`ifndef ( ZERO <-> ONE)
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"ok ( ZERO <-> ONE)"
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`endif
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`ifndef ( ONE <-> ZERO)
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"ok ( ONE <-> ZERO)"
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`endif
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`ifdef ( ONE <-> ONE)
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"ok ( ONE <-> ONE)"
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`endif
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`ifdef (ZERO)
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"bad"
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`elsif (ZERO)
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"bad"
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`elsif (ONE)
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"ok "
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`elsif (ONE)
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"bad"
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`endif
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// Did we end up right?
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Line: `__LINE__
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