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33 lines
735 B
Systemverilog
33 lines
735 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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`define DUP a
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`define DUP b_bad
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// verilator lint_off REDEFMACRO
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`define DUP c_nowarn
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// verilator lint_on REDEFMACRO
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`define DUP d_bad
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// verilator lint_save
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// verilator lint_off REDEFMACRO
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`define DUP e_nowarn
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// verilator lint_restore
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`define DUP f_bad
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/* verilator lint_off REDEFMACRO */
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`define DUP j_nowarn
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/* verilator lint_on REDEFMACRO */
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`define DUP k_bad
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/* verilator lint_save */
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/* verilator lint_off REDEFMACRO */
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`define DUP l_nowarn
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/* verilator lint_restore */
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`define DUP m_bad
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endmodule
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