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47 lines
1.3 KiB
Systemverilog
47 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2021 by Krzysztof Bieganski.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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package config_pkg;
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typedef struct packed {
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int UPPER0;
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int UPPER2;
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int USE_QUAD0;
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int USE_QUAD1;
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int USE_QUAD2;
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} config_struct;
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endpackage : config_pkg
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module t;
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import config_pkg::*;
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struct_submodule #(.MY_CONFIG('{
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UPPER0: 10,
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UPPER2: 20,
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USE_QUAD0: 4,
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USE_QUAD1: 5,
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USE_QUAD2: 6
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})) a_submodule_I ();
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endmodule : t
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module struct_submodule
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import config_pkg::*;
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#(parameter config_struct MY_CONFIG = '0);
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initial begin
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`checkd(MY_CONFIG.UPPER0, 10);
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`checkd(MY_CONFIG.USE_QUAD0, 4);
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`checkd(MY_CONFIG.USE_QUAD1, 5);
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`checkd(MY_CONFIG.USE_QUAD2, 6);
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`checkd(MY_CONFIG.UPPER2, 20);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule : struct_submodule
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