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38 lines
1.1 KiB
Systemverilog
38 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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parameter int SIZES [3:0] = '{1,2,3,4};
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typedef int calc_sums_t [3:0];
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function static calc_sums_t calc_sums;
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int sum = 0;
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for (int i=0; i<4; i++) begin
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sum = sum + SIZES[i];
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calc_sums[i] = sum;
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//TODO: calc_sums[i][31:0] = sum;
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end
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endfunction
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parameter int SUMS[3:0] = calc_sums();
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parameter int SUMS1[3:0] = calc_sums();
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initial begin
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if (SUMS[0] != 4) $stop;
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if (SUMS[1] != 4+3) $stop;
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if (SUMS[2] != 4+3+2) $stop;
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if (SUMS[3] != 4+3+2+1) $stop;
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// According to IEEE 1800-2023 13.4.3
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// execution at elaboration has no effect on the initial values
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// of the variables used either at simulation time or among
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// multiple invocations of a function at elaboration time
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if (SUMS1 != SUMS) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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