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32 lines
823 B
Systemverilog
32 lines
823 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// See issue #474
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package functions;
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localparam LP_PACK = 512;
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localparam LP_PACK_AND_MOD = 19;
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task check_param;
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$display("In %m\n"); // "In functions::check_param"
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if (LP_PACK_AND_MOD != 19) $stop;
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endtask
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endpackage
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module t ();
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// synthesis translate off
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import functions::*;
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// synthesis translate on
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localparam LP_PACK_AND_MOD = 20;
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initial begin
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// verilator lint_off STMTDLY
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#10;
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// verilator lint_on STMTDLY
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if (LP_PACK_AND_MOD != 20) $stop;
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check_param();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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