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25 lines
531 B
Systemverilog
25 lines
531 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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in
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);
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input int in;
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int ass_keptdead;
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initial begin
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if (in != 0) begin
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ass_keptdead = 1 | in;
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$display("Avoid gate removing");
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ass_keptdead = 2 | in;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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