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31 lines
566 B
Systemverilog
31 lines
566 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class EmptyClass_Dead;
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endclass
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module Mod_Dead;
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class ModClass_Dead;
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int memberb_dead;
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endclass
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endmodule
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//TODO dead check with class extends
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module t (/*AUTOARG*/);
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generate
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if (0) begin
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Mod_Dead cell_dead();
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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